1. Field of the Invention
The present invention relates to an optical transmission apparatus.
2. Description of the Related Art
In a redundant network configured according to a standard of optical transmission technology such as Synchronous Digital Hierarchy (SDH) or Synchronous Optical Network (SONET), a working line and a protection line are provided between two optical transmission apparatuses. Further, an Automatic Protection Switch (APS) function is provided for switching the working line to the protection line upon the occurrence of failure on the working line, so as to quickly respond to communication failure.
An example of such network configuration implementing the APS function is a network configuration called “1+1 APS” shown in FIGS. 7A to 7D. FIGS. 7A to 7D are schematic drawings for explaining the 1+1 APS.
In the “1+1 APS” as shown in FIGS. 7A to 7D, redundant lines are provided as a working line and a protection line between two optical transmission apparatuses. In the normal operation shown in FIG. 7A, an optical signal from an optical transmission apparatus on the left is forwarded to an optical transmission apparatus on the right over both the working line and the protection line, and a selector (see “SEL” of FIG. 7A) of the right optical transmission apparatus at the receiving end controls switching so as to receive the optical signal only from the working line. An optical signal from the right optical transmission apparatus is forwarded to the left optical transmission apparatus over both the working line and the protection line, and a selector of the left optical transmission apparatus at the receiving end controls switching so as to receive the optical signal only from the working line.
In the “1+1 APS”, upon occurrence of communication failure on the working line, a selector of an optical transmission apparatus controls switching so as to receive an optical signal from a neighboring optical transmission apparatus over the protection line. Specifically, as shown in FIG. 7B, switching is performed at the receiving end so that an optical signal sent over the protection line is received as well. In this way, communication failure can be quickly responded only by performing switching control at the receiving end.
After recovery from the communication failure, normal operation may be performed using the protection line as a working line and the recovered working line as a protection line as shown in FIG. 7C, or switching may be performed back again as shown in FIG. 7D.
Another example of the network configuration implementing the APS function is a ring network as shown in FIGS. 8A and 8B, so-called “Bidirectional Line Switch Ring (BLSR)” that performs switching control of the “1+1 APS”. FIGS. 8A and 8B are schematic drawings for explaining the BLSR.
In the normal operation of the “BLSR”, an optical signal is communicated using only one way of a communication path as a working direction. When communication failure occurs, the path direction used in the normal operation is switched to the reverse direction (protection direction) so that the communication failure can be quickly responded. As shown in FIG. 8A, for example, in the normal operation of the ring network including four optical transmission apparatuses, i.e. a node 1 to a node 4, an optical signal is sent from the node 4 to a node 2 using a path passing through a node 3.
In this state, when communication failure occurs between the node 4 and the node 3 as shown in FIG. 8B, the node 3 sends information of the communication failure to the node 4 through the node 2 and the node 1. In response to the information of the failure occurrence, the node 4 sends an optical signal to the node 2 using a reverse path direction (protection direction) of the current path direction. Specifically, the optical signal from the node 4 reaches the node 3 through the node 1 and the node 2, and turns around at the node 3 to be sent to the node 2.
In the “1+1 APS” or the “BLSR”, an optical transmission apparatus performs switching control of the APS function by exchanging with a neighboring optical transmission apparatus APS bytes (K1/K2 bytes) stored in the overhead of an SDH or a SONET optical signal. For example, when an optical transmission apparatus at the receiving end detects a failure such as a signal failure (SF) or signal degradation (SD), the apparatus notifies information of the failure to a neighboring apparatus using APS bytes storing such information, and performs switching control.
The switching control is performed within 50 milliseconds as required by the GR253 standard.
An example of an architecture realizing the “BLSR” is a centralized CPU (central processing unit) architecture as shown in FIG. 9. FIG. 9 is a schematic of a centralized CPU architecture.
As shown in FIG. 9, the centralized CPU architecture has a redundant configuration including: a CPU section that controls monitoring an entire optical transmission apparatus; and line interface units (LIUs), i.e., a WEST LIU and an EAST LIU, each having an interface function for external lines corresponding to working and protection lines.
Each of the WEST LIU and the EAST LIU includes hardware units. The hardware receives APS bytes over the working and the protection lines, and notifies information of SF and SD to the CPU section. The hardware also performs switching in response to a command from the CPU section. Each of the WEST LIU and the EAST LIU has a plurality of ports corresponding to the working and the protection lines.
In the centralized CPU architecture, firmware operating in a CPU of the CPU section collects information of the APS bytes from the WEST LIU and the EAST LIU, so as to control switching.
For example, when the hardware of the WEST LIU serving as an interface for the working line detects SF as a switching factor, the hardware notifies the occurrence of the SF to the firmware of the CPU section (see (1) shown in FIG. 9). The firmware of the CPU section then performs an APS determination process (switching determination process), based on the received SF information and the information of APS bytes from the WEST LIU (or a second LIU see (2) shown in FIG. 9), so as to control switching of the hardware in the WEST LIU and the EAST LIU (see (3) shown in FIG. 9). In this way, switching is performed as shown in FIG. 8B.
In the centralized CPU architecture, when the number of ports of an LIU increases or when a plurality of switching factors occur concurrently, the CPU section is congested with the APS determination process performed by the firmware, causing a problem that switching cannot be performed quickly for such a communication failure.
The problem is addressed with an architecture realizing a “BLSR”, such as a decentralized or distributed CPU architecture shown in FIG. 10. FIG. 10 is a schematic of a distributed CPU architecture.
As with the centralized CPU architecture, the distributed CPU architecture includes a CPU section, and a WEST LIU and an EAST LIU each having an interface function for external lines corresponding to the working and the protection lines, as shown in FIG. 10. Each of the WEST LIU and the EAST LIU includes a distributed CPU. Firmware operating in the CPU of one LIU collects information of APS bytes, and communicates it with firmware of the other LIU. Accordingly, information of both LIUs is shared to control switching.
In this arrangement, switching determination needs to be performed at either one of the redundant LIUs by referring to information of APS bytes sent over both the working and the protection lines. For example, a user of an optical transmission apparatus sets the CPU section to perform switching determination at the EAST LIU. The EAST LIU, when receiving the setting information through the firmware (user I/F section) of the CPU section, serves as a master CPU and dominantly controls switching of the hardware.
In the distributed CPU architecture, for example, when the hardware of the WEST LIU serving as an interface for the working line detects SF as a switching factor, it notifies the occurrence of the SF to the firmware in the CPU of the WEST LIU (see (1) shown in FIG. 10). The firmware of the WEST LIU notifies the occurrence of the switching factor to the firmware in the CPU (master CPU) of the EAST LIU by firmware communication (see (2) shown in FIG. 10). The firmware of the EAST LIU performs the APS determination process (switching determination process), based on the switching factor (SF) received from the WEST LIU and the information of APS bytes from the EAST LIU (see (3) shown in FIG. 10).
The firmware of the EAST LIU provides a result of the APS determination process as a switching notification to the firmware of the WEST LIU by firmware communication (see (4) shown in FIG. 10). Based on the result determined by the firmware of the EAST LIU, the firmware of the WEST LIU and the firmware of the EAST LIU control switching of the hardware of their respective LIUs (see (5) shown in FIG. 10). As such, switching is controlled based on the determination made by the CPU of the EAST LIU serving as a master CPU, and thus performed, for example, as shown in FIG. 8B.
Japanese Patent Application Publication No. H6-30002 discloses a programmable controller in which data is transferred by direct memory access (DMA) from a memory of a master CPU to a memory of a slave CPU, allowing the CPUs to share information
Japanese Patent Application Laid-open No. H8-202672 discloses a distributed multiprocessing system that includes processor units (a single master unit and a plurality of slave units) each including a CPU and a memory, and that allows the CPUs to share information by transferring data from the master unit to the slave units via a VERSA module Eurocard (VME) bus.
With the conventional technology, when failures occur concurrently on a plurality of ports of an LIU and thus switching is controlled, increased loads are placed on the process performed by the master CPU. As a result, switching cannot be performed quickly.
Specifically, in a configuration shown in FIGS. 11A and 11B, when switching control of the “BLSR” is performed by only a master CPU of an LIU, switching cannot be performed quickly within 50 milliseconds as required by the GR253 standard. FIGS. 11A and 11B are schematics for explaining a problem in a conventional configuration.
As shown in FIG. 11A, for example, when an LIU of an optical transmission apparatus (a distributed CPU architecture) realizing the “BLSR” has a redundant configuration including five physical ports, switching needs to be controlled by only a master CPU of one LIU based on APS information in combination of all the five ports.
When the “BLSR” is realized in a ring network including 16 nodes (each node represents an optical transmission apparatus) as shown in FIG. 11B, for example, a master CPU installed in an LIU of a node 1 having detected SF (signal failure) information of an optical signal from a node 16 completes switching control by performing a plurality of steps: controlling switching at the node 1 while providing a switching request to a node 2 to the node 16 and receiving a switching response from the node 2 to the node 16. Thus, the master CPU is required to have high processing capacity.
With the related art, for failures concurrently occurring on not more than four physical ports, for example, switching can be performed within 50 milliseconds by only a master CPU of one LIU. With an LIU having five or more physical ports as shown in FIG. 11A, however, switching cannot be performed within 50 milliseconds by only the master CPU to respond to failures concurrently occurring on all the physical ports.